1. Field of the Invention
The present invention relates to an ADIP decoder for decoding ADIP and an optical disc apparatus including the ADIP decoder.
2. Background Art
In recent years, recordable optical disc media have become widely available. For example, a DVD+R/RW medium, a recordable optical disc, includes tracks that are made up of recesses called grooves on a flat surface (land) of the disc. The grooves are so formed as to slightly wobble and a wobble signal (a signal varying in voltage according to the wobbling direction of the groove) having a predetermined period is extracted from the wobbling of the grooves.
In DVD+R/RW media, a wobble has a period 32 times as long as a channel bit that is the minimum unit of a recording signal.
Further, in DVD+R/RW media, a sector includes a frame (93-byte length)×26 as a data format and a wobble signal of 93 periods is allocated as a recording format to two frames.
Moreover, in DVD+R/RW media, address in pre-groove (ADIP) is formed in which the phase of a wobble signal is modulated to indicate physical positional information (address) on a disc.
ADIP is formed by providing 1-bit information in two frames and modulating the phases of the first eight periods in a wobble signal of 93 periods. A reproduced signal is read by four sectors, that is, 52 bits, so that a piece of address information is obtained.
Three modulation patterns of ADIP will now be examined. Of the modulation patterns, a sync pattern has a phase inversion point over the first four wobbles (will be referred to as 4T) and acts as an identification pattern indicating the first bit of the 52 bits. The other 51 bits contain a bit0 pattern or a bit1 pattern and form address information, physical information unique to a disc, and information bits including error correcting parity data.
For example, in both of the bit0 pattern and the bit1 pattern, the first wobble is phase inverted. Further, in the bit0 pattern, the seventh and eighth wobbles are phase inverted over two wobble periods. In the bit1 pattern, the fifth and sixth wobbles are phase inverted over two wobble periods (will be referred to as 2T).
For example, when non-inverted wobbles are represented as “0” and inverted wobbles are represented as “1” in the first eight periods in a wobble signal of 93 periods, the following patterns are obtained: sync pattern=“11110000”, bit0 pattern=“10000011” and bit 1 pattern=“10001100”.
Conventionally, optical disc apparatuses including circuits for decoding ADIP recorded in wobbles have been available. In such an optical disc apparatus, a wobble signal component is extracted by a matrix amplifier from a signal read from a pickup. The wobble signal is stabilized in the amplitude direction by automatic gain control (AGC) and then is inputted to an LPF and a BPF.
In the BPF, only a wobble frequency component is passed through a narrow band and a stable wobble signal is generated. From this signal, a clock with a stable wobble frequency is generated by a PLL circuit. This clock is used as a processing clock for decoding ADP. Further, during recording, this clock is used for generating a recording clock with high tracking capability relative to a disc rotation rate.
On the other hand, in the LPF, components that are higher than the wobble frequency and become noise to a wobble are removed. Such components include information recorded on a disc. After passing through the LPF, the wobble signal is binarized by a binarizing circuit having a proper slice level. A VCO included in a wobble PLL generates a phase and frequency locked clock (hereinafter, will be referred to as a locked wobble) and a clock shifted in phase by a quarter wobble from the locked wobble.
An output signal obtained by inputting the locked wobble and the binarized signal to an Exclusive OR circuit is synchronized by the quarter-delayed clock, so that an ADIP stream can be obtained in which an inverted wobble is represented as “1” and a non-inverted wobble is represented as “0”.
The ADIP stream is inputted to an ADIP synchronous demodulator circuit. The ADIP synchronous demodulator circuit performs pattern matching based on the inputted ADIP stream and detects the sync pattern, the bit0 pattern, and the bit1 pattern.
A wobble counter provided in the ADIP synchronous demodulator circuit detects the three patterns, so that eight wobbles indicating ADIP information are matched with the 0 to 7 phases of a scale-of-93 counter.
On the other hand, a line counter provided in the ADIP synchronous demodulator circuit counts up in response to the carry of the wobble counter and measures 52 lines, that is, an ADIP period of four sectors.
The line counter identifies an ADIP unit (that is, the boundary position of 52 bits) in response to the detection of the sync pattern and is reset to “0”. Then, a decoding pattern detected according to the value of the line counter undergoes serial-parallel (S/P) conversion in an ADIP demodulator provided in the ADIP synchronous demodulator circuit, so that ADIP demodulation results are obtained for four sectors.
Although the conventional ADIP decoding method can achieve a simple circuit configuration, this method has not reached a practical level for the following reasons:
The first reason is that the above-mentioned LPF has to have a cutoff frequency in a band higher than the wobble frequency to prevent a distorted waveform on an inverted part of ADIP. However, as described above, a wobble is generated in a period of 32 channel bits and in a band close to a recorded signal component.
Consequently, it is necessary to choose whether to increase the cutoff frequency of the LPF to obtain a wobble waveform with a small distortion or to remove a channel frequency component. Therefore, it is not possible to simultaneously obtain a waveform with a small distortion and remove a channel frequency component, so that it is difficult to keep a stable waveform.
In order to avoid this problem, a digital filtering method using an infinite impulse response (IIR) filter and the like is available. This method, however, complicates a circuit configuration and requires a higher sampling resolution, so that the current consumption may be increased.
Further, the waveform of an LPF path may have DC fluctuations due to the influence of crosstalk and the like. Even when, in order to absorb DC fluctuations, a signal is passed through a HPF having a cutoff frequency close to a wobble frequency band, the waveform is distorted. Therefore, it is necessary to choose whether to reduce the cutoff frequency to suppress the occurrence of a distorted waveform while accepting sharp DC fluctuations or to increase tracking capability while accepting a distorted waveform.
The second reason is that in the above-mentioned configuration of the optical disc apparatus, a phase delay varies between the LPF and the BPF due to device-to-device variation. Thus it is necessary to properly adjust the timing of both of the input signals in the Exclusive OR circuit.
Particularly, a recording clock is generated from the above-mentioned BPF and thus the BPF requires a narrow frequency band. Therefore, the phase shift inevitably becomes large when the center frequency of the frequency band is displaced.
When the cutoff frequency of the LPF is brought close to the wobble frequency band, phase characteristics abruptly change and thus the phase shift increases.
The phase delays of the BPF and the LPF are not equal to each other because the BPF and the LPF include different devices and signal paths. The difference in phase delay is also caused by a temperature change. Thus an adjustment may be necessary not only in the manufacturing process but also at the start or during reproduction on a disc. Consequently, the apparatus has poor performance.
Further, an optical disc apparatus is available which uses a technique proposed for improving decoding stability (e.g., see Japanese Patent Laid-Open No. 2004-103184). In this optical disc apparatus, the binarizing circuit of the above-mentioned conventional optical disc apparatus is changed to an analog-digital converter (ADC).
In this conventional optical disc apparatus, a wobble signal having passed through an LPF is inputted to the ADC.
On the other hand, a clock generated in the VCO of a wobble PLL is inputted to a timing generating circuit. The timing generating circuit generates the sampling timing signal of the ADC. The output result of the ADC is inputted to a Viterbi decoding circuit after passing through a digital filter. The Viterbi decoding circuit decodes ADIP by using partial response maximum likelihood (PRML) technique.
The sampling timing of the ADC is adjusted to the top of the wobble signal after filtering in the LPF. Then, this result is filtered through the above-mentioned digital filter to distinguish the singular point of an inverted part.
After that, an ADIP stream is obtained according to a defined Viterbi algorithm. The ADIP stream is determined after being displaced by several wobbles according to Viterbi processing.
This conventional technique can accurately decode ADIP even when waveform integrity deteriorates due to white noise and so on. However, when the sampling timing of the ADC is not properly adjusted and causes a timing delay, reading capability rapidly deteriorates.
Thus a timing adjusting process for compensating variations between the LPF and the BPF is necessary. Moreover, a large Viterbi processing circuit is required for increasing the accuracy of decoding and the circuit size may be increased. Further, the ADC has to be sampled twice for each wobble waveform and has to be operated at high speeds, so that the current consumption may be increased.